Transforming Squeezebox into High-end Transport

October 1, 2007

If you have a dac with a 11.2896mHz clock you are in luck! This project may summon your interest if you are searching for a high-end, affordable transport to serve as a bridge between your dac and music server. This implementation: (a) leverages Left Justified and I2S transmission, (b) eliminates SPDIF, (c) enhances decoupling between one’s DAC and file server by use of Ethernet relative to USB, and (d) results in very low jitter. There is at least one trade-off; namely, you will no longer be able to stream internet radio via your SB unless you add additional circuitry. The Squeezebox is modified to enable input of a high quality master clock that is output from your external DAC. The Squeezebox then outputs signals in Left Justified Format (the paternal twin of I2S so to speak) thereby eliminating the SPDIF interface from your entire digital chain. Because the DAC has a very low jitter oscillator that is fed to the Squeezebox, the SB signals are able to synchronize to the clock in the DAC. This enables use of a synchronous reclocking circuit located in the external DAC. The BCK, SDATA and LRCK signals are intercepted in the Squeezebox and output in Left Justified Format to the external DAC and converted to I2S on the new reclocking board. These signals then get reclocked in the DAC using the same low jitter clock. The Squeezebox takes a 3.3V logic signal. The reclocking board was designed by John Swenson who generously made this available on Slim Devices’ audiophile forum. He spec’d a 5V Tent XO and 5V Tent Shunt Regulator. This works for a DAC such as the TDA1541 which requires a 5V clock and accepts I2S input. However, in order to send the master clock to the Squeezebox, the circuit reduces the 5V Tent XO to 3.3V because the higher voltage would damage the SB. All credit goes to John Swenson!

Details about the Reclocking Circuit (a post by John Swenson on Slim Devices’ forum)

Note the circuit for shifting the data from left justified to I2S is a little complicated, this is to make sure that you don’t have a race condition at the input to the DAC. The basic concept is the data gets clocked by the bclk which shifts it over by one so its I2S spec. What this does is clock data by the reclocked bclk, then clock it again by a reclocked inverted bclk, then the output is reclocked again. The net result is that the delayed data has exactly the same timing in relation to the other signals as the original data has, thus almost guaranteeing you won’t have a timing problem.

The voltage conversion is done with HC logic run off 3.3V and because it is 5V tolerant it works fine with this. In this circuit John specified the Tent 5V shunt regulator to run everything except the inverters driving the SB3. You certainly can use another regulator, but using the Tent makes this really easy, its hard to design your own regulator that will work as well as this and cost significantly less.

Note I’m using a 174 to do the actual reclocking, this flies in the face all the conventional wisdom. There IS a reason for that. It depends on how you are building this. If you are using a PC board with SMD parts, the best way is the “pico gate” single gate chips, these work wonderfully well for this. If you are using through-hole parts and hand soldering things up I personally think the 174 is a better compromise. Because the DIP chips are so much larger they have much more capacitance and inductance on their package pins, using 4 or five of these will degrade the clock driving all of them worse than the jitter inside the one chip. Using 74s with both flops used is also not bad, that’s kind of a wash with the 174. I definitely would not use DIP 74s and only one flop per package. That sounds worse than a 174.

Link to Schematic

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